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| d a t a sh eet product speci?cation supersedes data of 1995 feb 15 file under integrated circuits, ic02 1996 mar 28 integrated circuits tda8762 10-bit high-speed low-power analog-to-digital converter
1996 mar 28 2 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 features 10-bit resolution sampling rate up to 40 mhz dc sampling allowed one clock cycle conversion only high signal-to-noise ratio over a large analog input frequency range (9.4 effective bits at 4.43 mhz full-scale input at f clk = 40 mhz) no missing codes guaranteed in range (ir) ttl output ttl compatible digital inputs and outputs low-level ac clock input signal allowed external reference voltage regulator power dissipation only 380 mw (typical) low analog input capacitance, no buffer amplifier required no sample-and-hold circuit required. applications high-speed analog-to-digital conversion for: video data digitizing radar pulse analysis transient signal analysis high energy physics research sd modulators medical imaging. general description the tda8762 is a 10-bit high-speed analog-to-digital converter (adc) for professional video and other applications. it converts the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 40 mhz. all digital inputs and outputs are ttl compatible, although a low-level sine wave clock input signal is allowed. quick reference data ordering information symbol parameter conditions min. typ. max. unit v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output stages supply voltage 4.4 5.0 5.25 v i cca analog supply current - 29 36 ma i ccd digital supply current - 24 30 ma i cco output stages supply current - 23 30 ma inl integral non-linearity f clk = 40 mhz; ramp input - 0.75 1.5 lsb dnl differential non-linearity f clk = 40 mhz; ramp input - 0.3 0.7 lsb f clk(max) maximum clock frequency 40 -- mhz p tot total power dissipation - 380 500 mw type number package sampling frequency (mhz) name description version tda8762m/4 ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 40 1996 mar 28 3 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 block diagram fig.1 block diagram. handbook, full pagewidth 12 dgnd 5 6 8 r lad 7 9 agnd2 v rb v rm v rt v i 11 v ccd 3 26 v cca 21 22 23 24 20 d4 d5 d6 d7 d8 19 18 25 2 d3 d2 17 d1 16 d0 d9 in range latch ttl outputs latches analog -to - digital converter clock driver mgc035 ttl output 1 clk 10 oe tc tda8762 13 v cco1 4 agnd1 analog grounds digital ground 27 ognd2 14 ognd1 output grounds analog voltage input data outputs lsb msb 28 v cco2 ir output 1996 mar 28 4 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 pinning symbol pin description clk 1 clock input tc 2 twos complement input (active low) v cca 3 analog supply voltage (+5 v) agnd1 4 analog ground 1 agnd2 5 analog ground 2 v rb 6 reference voltage bottom input v rm 7 reference voltage middle v i 8 analog input voltage v rt 9 reference voltage top input oe 10 output enable input (ttl level input, active low) v ccd 11 digital supply voltage (+5 v) dgnd 12 digital ground v cco1 13 supply voltage for output stages 1 (+5 v) ognd1 14 output ground 1 n.c. 15 not connected d0 16 data output; bit 0 (lsb) d1 17 data output; bit 1 d2 18 data output; bit 2 d3 19 data output; bit 3 d4 20 data output; bit 4 d5 21 data output; bit 5 d6 22 data output; bit 6 d7 23 data output; bit 7 d8 24 data output; bit 8 d9 25 data output; bit 9 (msb) ir 26 in range data output ognd2 27 output ground 2 v cco2 28 supply voltage for output stages 2 (+5 v) fig.2 pin configuration. handbook, halfpage 1 2 3 4 5 6 7 8 9 10 11 12 13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 clk tc cca agnd1 agnd2 rb rm i rt oe ccd dgnd cco1 ognd1 cco2 ognd2 ir d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 n.c. v v v v v v v v tda8762 mgc036 1996 mar 28 5 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 limiting values in accordance with the absolute maximum rating system (iec 134). note 1. the supply voltages v cca , v ccd and v cco may have any value between - 0.3 v and +7.0 v provided that the supply voltage differences d v cc are respected. handling inputs and outputs are protected against electrostatic discharges in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. thermal characteristics symbol parameter conditions min. max. unit v cca analog supply voltage note 1 - 0.3 +7.0 v v ccd digital supply voltage note 1 - 0.3 +7.0 v v cco output stages supply voltage note 1 - 0.3 +7.0 v d v cc supply voltage difference v cca - v ccd - 1.0 +1.0 v v cca - v cco - 1.0 +1.0 v v ccd - v cco - 1.0 +1.0 v v i input voltage referenced to agnd - 0.3 +7.0 v v clk(p-p) ac input voltage for switching (peak-to-peak value) referenced to dgnd - v ccd v i o output current - 10 ma t stg storage temperature - 55 +150 c t amb operating ambient temperature 0 +70 c t j junction temperature - +150 c symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 110 k/w 1996 mar 28 6 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 characteristics v cca =v 3 to v 4 and v 5 = 4.75 to 5.25 v; v ccd =v 11 to v 12 = 4.75 to 5.25 v; v cco =v 13 and v 28 to v 14 and v 27 = 4.4 to 5.25 v; agnd and dgnd shorted together; t amb = 0 to +70 c; typical values measured at v cca =v ccd =v cco =5v; v i(p-p) = 2.0 v; c l = 15 pf and t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output stages supply voltage 4.4 5.0 5.25 v d v cc voltage difference v cca - v ccd - 0.25 - +0.25 v v cca - v cco - 0.4 - +0.4 v v ccd - v cco - 0.4 - +0.4 v i cca analog supply current - 29 36 ma i ccd digital supply current - 24 30 ma i cco output stages supply current c l = 15 pf; ramp input - 23 30 ma inputs c lock input clk ( referenced to dgnd); note 1 v il low level input voltage 0 - 0.8 v v ih high level input voltage 2.0 - v ccd v i il low level input current v clk = 0.4 v - 10 +1 m a i ih high level input current v clk = 2.7 v -- 20 m a z i input impedance f clk = 40 mhz - 2 - k w c i input capacitance f clk = 40 mhz - 2 - pf i nputs oe and tc ( referenced to dgnd); see table 2 v il low level input voltage 0 - 0.8 v v ih high level input voltage 2.0 - v ccd v i il low level input current v il = 0.4 v - 400 -- m a i ih high level input current v ih = 2.7 v -- 20 m a v i ( analog input voltage referenced to agnd) i il low level input current v i = 1.3 v - 0 -m a i ih high level input current v i = 3.8 v - 70 -m a z i input impedance f i = 4.43 mhz - 5 - k w c i input capacitance f i = 4.43 mhz - 8 - pf 1996 mar 28 7 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 reference voltages for the resistor ladder; see table 1 v rb reference voltage bottom 1.2 1.3 - v v rt reference voltage top - 3.8 v cca - 0.8 v v v diff differential reference voltage v rt - v rb 1.8 2.5 3.0 v i ref reference current - 28 - ma r lad resistor ladder - 90 -w tc rlad temperature coef?cient of the resistor ladder - 1860 - ppm - 167 - m w /k v osb offset voltage bottom note 2 - 220 - mv v ost offset voltage top note 2 - 220 - mv v i(p-p) analog input voltage (peak-to-peak value) note 3 1.5 2.06 2.5 v outputs d igital outputs d9 to d0 and ir ( referenced to ognd) v ol low level output voltage i o = 1 ma 0 - 0.4 v v oh high level output voltage i o = 0 ma 2.7 - v cco - 0.5 v i o = - 0.4 ma 2.7 - v cco - 1.3 v i o = - 1 ma 2.4 - v cco - 1.4 v i oz output current in 3-state mode 0.4 v < v o 1996 mar 28 9 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 notes 1. in addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 0.5 ns. 2. analog input voltages producing code 0 up to and including code 1023: a) v osb (voltage offset bottom) is the difference between the analog input which produces data equal to 00 and the reference voltage bottom (v rb ) at t amb =25 c. b) v ost (voltage offset top) is the difference between v rt (reference voltage top) and the analog input which produces data outputs equal to code 1023 at t amb =25 c. 3. in order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to pins v rb and v rt via offset resistors r ob and r ot as shown in fig.3. a) the current flowing into the resistor ladder is i l = and the full-scale input range at the converter, to cover code 0 to code 1023, is . . b) since r l , r ob and r ot have similar behaviour with respect to process and temperature variation, the ratio will be kept reasonably constant from part to part. consequently variation of the output codes at a given input voltage depends mainly on the difference v rt - v rb and its variation with temperature and supply voltage. when several adcs are connected in parallel and fed with the same reference source, the matching between each of them is then optimized. 4. . d ifferential gain ; note 9 g diff differential gain f clk = 40 mhz; pal modulated ramp - 0.5 - % d ifferential phase ; note 9 j diff differential phase f clk = 40 mhz; pal modulated ramp - 0.5 - deg timing (f clk = 40 mhz; c l = 15 pf); see fig.4; note 10 t ds sampling delay time -- 2ns t h output hold time 5 -- ns t d output delay time - 10 14 ns c l digital output load - 15 40 pf 3-state output delay times; see fig.5 t dzh enable high - 45 50 ns t dzl enable low - 25 35 ns t dhz disable high - 12 15 ns t dlz disable low - 12 15 ns symbol parameter conditions min. typ. max. unit v rt v rb C r ob r l r ot ++ ----------------------------------------- - v i r l i l r l r ob r l r ot ++ ----------------------------------------- - v rt v rb C () 0.824 v rt v rb C () = = = r l r ob r l r ot ++ ----------------------------------------- ger v 1023 v 0 C () 2v C 2v ------------------------------------------------ 100 = 1996 mar 28 10 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 5. the analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device. no glitches greater than 2 lsbs, neither any significant attenuation are observed in the reconstructed signal. 6. the analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square-wave signal) in order to sample the signal and obtain correct output data. 7. effective bits are obtained via a fast fourier transform (fft) treatment taking 8k acquisition points per equivalent fundamental period. the calculation takes into account all harmonics and noise up to half of the clock frequency (nyquist frequency). conversion to signal-to-noise ratio: s/n = eb 6.02 + 1.76 db. 8. intermodulation measured relative to either tone with analog input frequencies of 4.43 mhz and 4.53 mhz. the two input signals have the same amplitude and the total amplitude of both signals provides full scale to the converter. 9. measurement carried out using video analyser vm700a, where the video analog signal is reconstructed through a digital-to-analog converter. 10. output data acquisition: the output data is available after the maximum delay time of t d . fig.3 explanation of note 3. handbook, halfpage r lad r ot v rt v rm v rb r ob code 1023 code 0 mgd281 i l r l 1996 mar 28 11 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 table 1 output coding and input voltage (typical values; referenced to agnd, v rb = 1.3 v, v rt = 3.8 v) table 2 mode selection step v i(p-p) ir binary output bits twos complement output bits d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 u/f < 1.52 0 00000000001000000000 0 1.52 1 00000000001000000000 1 . 100000000011000000001 . . ..................... . . ..................... 1022 . 111111111100111111110 1023 3.58 1 11111111110111111111 o/f > 3.58 0 11111111110111111111 tc oe d9 to d0 ir x 1 high impedance high impedance 0 0 active; twos complement active 1 0 active; binary active fig.4 timing diagram. handbook, full pagewidth ds t sample n + 1 sample n clk mgc037 sample n + 2 1.4 v v l data d0 to d9 t d t h cph t cpl t 2.4 v 0.4 v 1.4 v data n + 1 data n data n - 1 data n - 2 1996 mar 28 12 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 fig.5 timing diagram and test conditions of 3-state output delay time. handbook, full pagewidth mgc038 50 % 50 % high low dzh t dhz t 50 % high low dzl t dlz t 10 % 90 % output data v ccd output data 3.3 k w 15 pf s1 v ccd tda8762 oe oe test dlz t dzl t dhz t dzh s1 ccd v ccd v gnd gnd t f oe = 100 khz. 1996 mar 28 13 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 fig.6 analog input settling-time diagram. handbook, full pagewidth mgd345 50 % stlh t 2 ns code 0 code 1023 i 50 % 0.5 ns 50 % 2 ns sthl t 50 % 0.5 ns clk v fig.7 fast fourier transform (f clk = 40 mhz; f i = 4.43 mhz). effective bits: 9.46; thd = - 71.19 db; harmonic levels (db): 2nd = - 79.70; 3rd = - 72.84; 4th = - 81.54; 5th = - 83.93; 6th = - 86.47. handbook, full pagewidth 20 0 120 0 5 7.5 10 15 17.5 2.5 12.5 mlc947 40 80 100 60 20 a (db) f (mhz) 1996 mar 28 14 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 fig.8 fast fourier transform (f clk = 40 mhz; f i = 10 mhz). effective bits: 9.11; thd = - 63.18 db; harmonic levels (db): 2nd = - 66.49; 3rd = - 66.52; 4th = - 85.15; 5th = - 75.95; 6th = - 83.47. handbook, full pagewidth 20 0 120 0 5 7.5 10 15 17.5 2.5 12.5 mlc948 40 80 100 60 20 a (db) f (mhz) fig.9 fast fourier transform (f clk = 40 mhz; f i = 15 mhz). effective bits: 8.70; thd = - 60.18 db; harmonic levels (db): 2nd = - 62.24; 3rd = - 70.44; 4th = - 77.29; 5th = - 65.99; 6th = - 89.67. handbook, full pagewidth 20 0 120 0 5 7.5 10 15 17.5 2.5 12.5 mlc949 40 80 100 60 20 a (db) f (mhz) 1996 mar 28 15 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 internal pin configurations fig.10 ttl data and in-range outputs. handbook, halfpage mgc039 ognd1 d9 to d0 ir v cco1 v cco2 fig.11 analog inputs. handbook, halfpage mgc040 - 1 agnd v cca v i fig.12 oe ( tc) input. handbook, halfpage mgd344 ognd2 v cco1 (tc) oe fig.13 v rb , v rm and v rt . r mbe565 v rb v rm v cca agnd v rt lad 1996 mar 28 16 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 fig.14 clk input. handbook, halfpage v v ccd clk dgnd mgc042 - 1 ref (1.3 v) 1996 mar 28 17 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 application information additional application information will be supplied upon request (please quote number an96025 ). fig.15 application diagram. the analog and digital supplies should be separated and decoupled. the external voltage reference generator must be built such that a good supply voltage ripple rejection is achieved with respec t to the lsb value. eventually, the reference ladder voltages can be derived from a well regulated v cca supply through a resistor bridge and a decoupled capacitor. (1) v rb , v rm and v rt are decoupled to agnd. (2) pin 15 should be connected to dgnd in order to prevent noise influence. (3) when v rm is not used, pin 7 can be left open, avoiding the decoupling capacitor. in any case, this pin must not be grounded. (4) when analog input signal is ac coupled, an input bias or a clamping level must be applied to v i input (pin 8). handbook, halfpage 28 27 26 25 24 23 22 21 20 19 18 17 tda8762 ognd2 v cco1 d3 d4 d5 d6 d7 d8 d9 d2 d1 d0 v ccd v cca 1 2 3 4 5 6 7 8 9 10 11 12 clk agnd1 agnd2 n.c. v rb v rm v rt mgc043 16 15 13 14 100 nf 100 nf dgnd ognd1 ir oe tc v cco2 agnd agnd 100 nf agnd v i (1) (3)(1) (1) (4) (2) 1996 mar 28 18 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 package outline unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 1.1 0.7 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 1.03 0.63 sot341-1 mo-150ah 93-09-08 95-02-04 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 114 28 15 0.25 y pin 1 index 0 2.5 5 mm scale ssop28: plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 a max. 2.0 1996 mar 28 19 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all ssop packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for ssop packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. even with these conditions, only consider wave soldering ssop packages that have a body width of 4.4 mm, that is ssop16 (sot369-1) or ssop20 (sot266-1) . during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 1996 mar 28 20 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. 1996 mar 28 21 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 notes 1996 mar 28 22 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 notes 1996 mar 28 23 philips semiconductors product speci?cation 10-bit high-speed low-power analog-to-digital converter tda8762 notes philips semiconductors C a worldwide company argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. (02) 805 4455, fax. (02) 805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. (01) 60 101-1256, fax. (01) 60 101-1250 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. (172) 200 733, fax. (172) 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. (359) 2 689 211, fax. (359) 2 689 102 canada: philips semiconductors/components: tel. (800) 234-7381, fax. (708) 296-8556 chile: see south america china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. (852) 2319 7888, fax. (852) 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (032) 88 2636, fax. (031) 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. (358) 0-615 800, fax. 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(02) 709-1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03) 750 5214, fax. (03) 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. 9-5(800) 234-7831, fax. (708) 296-8556 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. (040) 2783749, fax. (040) 2788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09) 849-4160, fax. (09) 849-7811 norway: box 1, manglerud 0612, oslo, tel. (022) 74 8000, fax. (022) 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (63) 2 816 6380, fax. (63) 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. (022) 612 2831, fax. (022) 612 2327 portugal: see spain romania: see italy singapore: lorong 1, toa payoh, singapore 1231, tel. (65) 350 2000, fax. (65) 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. (011) 470-5911, fax. (011) 470-5494 south america: rua do rocio 220 - 5th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil, p.o. box 7383 (01064-970), tel. (011) 821-2333, fax. (011) 829-1849 spain: balmes 22, 08007 barcelona, tel. (03) 301 6312, fax. (03) 301 4107 sweden: kottbygatan 7, akalla. s-16485 stockholm, tel. (0) 8-632 2000, fax. (0) 8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01) 488 2211, fax. (01) 481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1, p.o. box 22978, taipei 100, tel. (886) 2 382 4443, fax. (886) 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. (66) 2 745-4090, fax. (66) 2 398-0793 turkey : talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0212) 279 2770, fax. (0212) 282 6707 ukraine: philips ukraine, 2a akademika koroleva str., office 165, 252148 kiev, tel. 380-44-4760297, fax. 380-44-4766991 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181) 730-5000, fax. (0181) 754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800) 234-7381, fax. (708) 296-8556 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. (381) 11 825 344, fax. (359) 211 635 777 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31-40-2724825 scds48 ? philips electronics n.v. 1996 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 537021/1100/02/pp24 date of release: 1996 mar 28 document order number: 9397 750 00767 |
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